In recent years, the transition to high-density mounting of electronic components assembled in an electronic equipment has been rapidly advanced to meet the demands for improved performance and reduced size of electronic equipment. To comply with the requirements of such a transition to high-density mounting, semiconductor chips are sometimes surface mounted on a wiring board via bumps in a bare chip state, that is, flip-chip mounting is sometimes conducted. As for the wiring boards for mounting the semiconductor chips, following the transition to multi-terminal semiconductor chips, buildup multilayer wiring boards that are advantageous in terms of attaining high-density wiring are sometimes employed. Such semiconductor chips or buildup multilayer wiring boards are described, for example, in Japanese Patent Application Laid-open No. S58-157146 and “High-Performance Flip-Chip BGA Based on Multi-Layer Thin-Film Packaging Technology” (Tadanori SHIMOTO et al., Proceedings of the 2002 International Microelectronics and Packaging Society, pp. 10-15).
With the conventional method for flip-chip mounting a semiconductor chip on a wiring boards, first, a plurality of solder bump electrodes are formed on the prescribed surface of the chip. Meanwhile, a solder paste is printed on the electrode pads for external connection that are present on the wiring boards. Then, the chip is placed on the wiring board so that the solder bump electrodes of the chip are abutted against the solder paste on the electrode pads in the wiring board. Then, the semiconductor chip and wiring board are heated to a temperature equal to or higher than the melting point of the solder material in a reflow furnace, followed by cooling. In the cooling process, the solder material solidifies and the chip and electrode pads are soldered together.
Thermal expansion coefficient in the plane-spread direction in a semiconductor chip composed of a general semiconductor base material is about 3-5 ppm/° C., the thermal expansion coefficient in the plane-spread direction in a typical wiring board employing a glass epoxy substrate as a core board is about 10-20 ppm/° C., and the difference between the two thermal expansion coefficients is comparatively large. Moreover, when the wiring board has a buildup multilayer wiring structure, the thermal expansion coefficient in the plane-spread direction of the buildup multilayer wiring structure is 15-25 ppm/° C. and the difference in thermal expansion coefficient between the buildup multilayer wiring structure and the chip is rather large.
For this reason, after the chip and wiring board pass through the same peak temperature in the flip-chip mounting process and reach a normal temperature, inappropriate warping or waving occurs, in particular, in the wiring board and stresses easily appear in the electric connection portion between the chip and wiring board due to the difference in thermal expansion coefficient between the chip and wiring board. If stresses exceeding the prescribed level appear in the electric connection portion, cracking or peeling easily occurs at the interface of the bump electrodes of the chips and electrode pads of the wiring board in the connection portion. Such an inconvenience tends to be especially significant when a semiconductor chip is flip-chip mounted on a buildup multilayer wiring structure, which has no core board, or when a semiconductor chip is flip-chip mounted on a zone that is not in contact with the core board in the buildup multilayer wiring structure in the wiring board having the buildup multilayer wiring structure.